Quad Tile Intel Xe-HP GPU

At past week’s Intel Architecture Day, Intel’s main architect, Raja Koduri, briefly held up the smallest member of the company’s forthcoming Xe-HP series of server CPUs, the a person tile configuration. Now, only a number of days afterwards, he has upped the ante by displaying off the premier, 4 tile configuration.

Built to be a scalable chip architecture, Xe-HP is set to be available with just one, two, or 4 tiles. And though Intel has however to disclose also substantially in the way of details on the architecture, based mostly on their packaging disclosures it appears to be like like the enterprise is making use of their EMIB tech to wire up the GPU tiles, as perfectly as the GPU’s on-bundle HBM memory.

Assuming it helps make it to sector, a multi-tiled GPU – in essence many GPUs in a single package – would be a major accomplishment for Intel. GPUs are notoriously bandwidth-hungry due to the require to shovel facts all over between cores, caches, and command frontends, which helps make them non-trivial to break up up in a chiplet/tiled manner. Even if Intel can only use this form of multi-tile scalability for compute workloads, that would have a substantial impression on what sort of general performance a one GPU package deal can achieve, and how future servers may well be created.